This invention relates to a dry etching method and, more particularly, to a method employed during etching for forming a connection hole in a silicon compound insulating film on an Al based interconnection layer for preventing the underlying Al-based interconnection layer from being sputtered off and re-deposited on the sidewall surface of the connection hole.
In a semiconductor device with a high integration degree and a high device density, such as VLSIs or ULSIs of recent origin, the proportion of the interconnection on a device chip has become higher. In order to prevent the resulting increase in the chip size, a multilevel interconnection process has become an indispensable technique. In the multilevel interconnection process, it is necessary to bore a through-hole in an interlayer insulating film between an upper interconnection layer and a lower interconnection layer as a via-hole for establishing electrical connection between the two layers.
As a material for the interlayer insulating film, a silicon oxide (SiO.sub.x) based material is employed. The etching of an SiC.sub.x based material layer is generally carried out under conditions of producing a high incident ion energy for severing its strong Si-O bonds. That is, the etching mechanism of the SiO.sub.2 material layer is comparable to a physical process, such as sputtering, rather than a chemical process, such as radical reaction.
Meanwhile, with an etching process accompanied by strong ion impact, the problem of the lowering of underground selectivity is presented inevitably. Above all, if a layer of the interconnection material susceptible to sputtering, such as the layer of the Al-based material, is present in the multilevel interconnection structure as an underlying layer for the insulating film, the surface of the interconnection material layer is sputtered and reduced in film thickness. Besides, products of the sputtering tend to be re-deposited on the inner wall surface of the via-hole to produce various problems.
The manner of the re-deposition in case the interconnection material layer is an Al-based material is explained by referring to FIGS. 1A to 1C. FIG. 1A shows a resist mask 13 formed on an SiO.sub.2 interlayer insulating film 12 deposited on an Al-based interconnection layer 11. An opening 14 is formed in the resist mask 13 in accordance with a hole pattern.
It is now assumed that the SiO.sub.2 interlayer insulating film 12 is etched under this condition to form a via-hole 15. The etching is performed in general under a higher incident energy condition and the underlying Al-based interconnection layer 11 is a layer of a material having a high sputtering rate. Consequently, the slightest overetching results in the exposed surface of the Al-based Interconnection layer 11 being sputtered, with the sputtered product being deposited on the sidewall surface of the via-hole 15 to form a re-deposited layer 16.
The re-deposited layer 16 is very difficult to remove and, even after removing the resist pattern 14 by ashing, the layer 16 is left in a state of being projected from an opening end of the via-hole 15, as shown in FIG. 1C. If a wafer is observed from its upper surface with an electron microscope, the re-deposited layer 16 looks like a royal crown, so that it is termed an aluminum crown.
The re-deposited layer 16, if peeled off or destroyed only partially, becomes a source of dust. Besides, if the layer 16 is protruded more or less from the upper most surface of the interlayer insulating film 12, an overlying layer tends to be affected in coverage to lower the yield of the semiconductor device significantly.
For preventing the underlying layer from being sputtered off as described above, a variety of methods have hitherto been proposed as countermeasures. One of these methods is to adopt an operating condition including a low self-bias potential Y.sub.dc, while another method consists in adding a compound capable of etching the underlying layer of the interconnection material during overetching to the etching gas. Still another method consists in using a tapered cross-sectional shape of the via-hole.
Of these, the method of using a tapered cross-sectional shape of the via-hole is discussed in detail in Extended Abstract of 1990 Dry Process Symposium, pages 105 to 109, title number V-3. The etching of the SiO.sub.2 interlayer insulating film is performed using a CHF.sub.3 gas as the wafer is cooled to a temperature of approximately -5.degree. C. In other words, the etching proceeds as the effective mask width is perpetually increased by the deposition of an excess carbonaceous polymer, so that the via-hole presents an inclined sidewall surface. Since the sidewall is inclined in this manner, it becomes possible for the ions to be incident on the inclined surface, so that, even when the sputtering product derived from the underlying Al-based interconnection layer is re-deposited on the surface, it can be removed instantly. On the other hand, since the particles of the sputtering product are incident on such inclined surface at a small angle of incidence, the re-deposition itself is hardly produced.
However, the above-mentioned countermeasures are not without problems.
First, the method of lowering the self-bias potential V.sub.dc consists in lowering the incident ion energy to prevent incidental removal of the underlying interconnection layer. However, with the dry etching of recent origin, the prevalent concept is to achieve substantial anisotropy using a low pressure discharge plasma. As compared to the ion density in the conventional RF plasma, the ion density in the low pressure discharge plasma tends to be decreased because the ion density is acutely lowered in the RF plasma with decrease in the gas pressure. Consequently, this method is not effective to achieve a practically useful etch rate or throughput with the layer of the silicon compound for which an etching mechanism is based essentially on an ion-assisted reaction. While it is possible to accelerate the ions intentionally by increasing the input power or the substrate bias, the substrate tends to be damaged by the high energies afforded to the ions in this manner.
With the method of using a gas capable of etching the underlying interconnection material layer during overetching, it is possible to prevent the re-deposition. However, since the layer of the interconnection material is removed simultaneously, the aspect ratio of the via-hole is increased so that difficulties are raised in the subsequent plugging of the via-hole. In extreme cases, the layer of the interconnection material may be removed and eventually lost.
On the other hand, with the technique of providing a tapered cross-sectional shape of the via-hole, an excess amount of the carbonaceous polymer needs to be generated for achieving a significant taper, so that there is the risk of the particle level becoming undesirable. There is also raised another problem that the contact resistance between the layer of the electrically conductive material buried in the via-hole and the underlying layer of the interconnection material is increased because the bottom surface of the via-hole becomes narrower than the opening area in the mask.
Consequently, one has to make an extremely difficult selection of adopting an anisotropic cross-sectional shape of the via-hole and of achieving a practically useful etch rate while preventing wasteful etching, re-deposition or damage done to the underlying interconnection layer.
For overcoming the above-mentioned difficulties, what may be demanded most strongly of the low-pressure discharge plasma includes an improved ionization ratio and controllability of the incidention energy.